Field of the Invention
The present invention relates generally to a non volatile memory device for multi-level charge storage. In particular, a device and a method for multilevel charge storage and an apparatus and a method for reading out from the storage device is disclosed.
Description of the Related Art
Non-volatile semiconductor memory devices are an important class of solid-state memory devices. A particular type of non-volatile semiconductor memory devices are flash EEPROM devices. The primary mechanism by which data are stored in a non-volatile memory device is by access to a memory cell. The demand for high-density Flash EEPROM memory devices in portable computing and telecommunication applications stimulates continuous efforts on scaling of flash EEPROM memory cell size. In order to further increase the storage capability of Flash memory devices, Multi-Level Charge Storage (MLCS) techniques have been developed. These techniques allow further reductions in the cost per bit of information of flash EEPROM non-volatile memory devices.
Typically, a MLCS memory device is configured such that 2.sup.n different charge levels, corresponding to threshold voltage levels, can be stored in one memory cell and the current corresponding to these different threshold voltage levels can be read-out. Thus, storage and read-out of n bits of data (with n being larger than or equal to two) in a single memory cell can be achieved. The cost per bit of information with MLCS techniques is reduced as a number related to 1/n.
Multi-level storage or write or progammation circuits and techniques, and read-out circuits and techniques have been disclosed. U.S. Pat. No. 5,043,940 of Harrari discloses a split-channel EEPROM device that can be programmed in more than two programmable threshold states. U.S. Pat. No. 4,771,404 of Mano et al. discloses a memory device which has memory cells capable of storing ternary or more information. This memory device includes a multilevel detector for detecting the information of the memory cells at one time and a reference generator for generating reference levels therefor. U.S. Pat. No. 5,163,021 of Mehrotra et al. discloses improvements in the Circuits and Techniques for read, write and erase of Multi-State EEPROM memory devices, the improved circuits making the reading relative to a set of threshold levels as provided by a corresponding set of reference cells. U.S. Pat. No. 4,415,992 discloses a read-out scheme for discriminating n charge levels of a memory cell in which (n-1) comparators and (n-1) voltage references are used in parallel to determine the charge level of the memory cell. Additional decoding logic is required to translate the outputs of the comparators into bits. A total of (2n - 1) different voltage amplitudes are necessary, and have to be implemented on chip. Other multilevel storage memory devices and programming methods have been disclosed in PCT published application WO95/34074, U.S. Pat. No. 5,422,845 and PCT published patent application WO95/34075.
A main disadvantage applying to the memory devices disclosed in the prior art is that they, in functioning, make use of a bit-by-bit program verification procedure. This procedure suffers from trade-offs between accuracy of the stored levels and programming speed. Consequently the programming operation slows down. Moreover, the chip implementation of the verification procedure increases the chip dimensions. Furthermore, the memory devices reported in the prior art employ read-out circuits based on a plurality of comparators and decoding logic which not only increase the complexity of the memory device but also enlarge the chip dimensions.
The prior art memory cells for multi-level charge storage employ programming methods based on either Fowler Nordheim Tunneling (FNT) or Channel Hot Electron (CHE) injection. The prior art multi-level programmming methods utilize a `program verify scheme` comprising the following common steps:
(1) A programming pulse of typically 100 microseconds to 1 millisecond duration is applied to the memory cell to be programmed; PA1 (2) The drain current of the memory cell to be programmed is sensed and presented to a comparator circuit which also has presented to it the current of a reference current source corresponding to one of the multilevel charge levels to which the cell has to be programmed; PA1 (3) If the current of the memory cell and the current of the reference current source match, then the cell is in the correct state and no further programming is required. If however the currents do not match, then steps (1) and (2) are repeated.
The prior art programming methods fail to disclose a MLCS method characterized by high programming speed and small chip'size required to implement the memory device. Since according to the prior art programming methods several iterations of the programming steps are required, and after each step a sensing step is required in order to accurately program the cell to the intended charge level, the speed of the entire programming operation is significantly compromised. The speed furthermore is a function of the particular charge level that has to be programmed. These disadvantages considerably decrease the data throughput of the memory device. The second problem has to do with silicon area consumption, since the silicon implementation of the `program verify scheme` increases the chip size.